library ieee;
use IEEE.std_logic_1164.all;

entity neg_instr is
  port(
		din         : in    std_logic_vector (7 downto 0);
		dout        : out   std_logic_vector (7 downto 0);
		flagi       : out   std_logic_vector (3 downto 0)
  );
end neg_instr;


architecture neg_instr_arch of neg_instr is

  component xor2 
    port (
          a : in  std_logic;
          b : in  std_logic;
          y : out std_logic
        
    );
end component;

component and2
    port (a, b : in std_logic;
       y : out std_logic);
end component and2;

signal nsf,cf,sf,ov,zf,c2,c3,c4,c5,c6,c7,ndin1,ndin2,ndin3,ndin4,ndin5,ndin6,ndin7,ndin0 : std_logic;

begin
		
		ndin0<= not din(0);
		ndin1<= not din(1);
		ndin2<= not din(2);
		ndin3<= not din(3);
		ndin4<= not din(4);
		ndin5<= not din(5);
		ndin6<= not din(6);
		ndin7<= not din(7);
		dout(0)<=din(0);
		
		and_1    :  and2 port map (
                                      a => ndin1,
                                      b => ndin0,
                                      y => c2
                                 );
                                 
		and_2    :  and2 port map (
                                      a => ndin2,
                                      b => c2,
                                      y => c3
                                 );
 		and_3    :  and2 port map (
                                      a => ndin3,
                                      b => c3,
                                      y => c4
                                 );

		and_4    :  and2 port map (
	                                    a => ndin4,
                                      b => c4,
                                      y => c5
                                 );
                                 
		and_5    :  and2 port map (
                                      a => ndin5,
                                      b => c5,
                                      y => c6
                                 );
		and_6    :  and2 port map (
                                      a => ndin6,
                                      b => c6,
                                      y => c7
                                 );

		and_7    :  and2 port map (
                                      a => c7,
                                      b => ndin7,
                                      y => cf
                                 );
                                                                 
		xor_1    :  xor2 port map (
		              
  
                                      a => ndin1,
                                      b => ndin0,
                                      y => dout(1)
                                    );

      xor_2    :  xor2 port map (
                                      a => ndin2,
                                      b => c2,
                                      y => dout(2)
                                    );

      xor_3    :  xor2 port map (
                                           
                                      a => ndin3,
                                      b => c3,
                                      y => dout(3)
                                    );

      xor_4    :  xor2 port map (
                                      a => ndin4,
                                      b => c4,
                                      y => dout(4)
                                    );
                                    
      xor_5    :  xor2 port map (
                                      a => ndin5,
                                      b => c5,
                                      y => dout(5)
                                    );
                                    
      xor_6    :  xor2 port map (
                                      a => ndin6,
                                      b => c6,
                                      y => dout(6)
                                    );
      xor_7    :  xor2 port map (
                                      a => c7,
                                      b => ndin7,
                                      y => sf
                                    );
      
      and_zf    :  and2 port map (
                                      a => ndin7,
                                      b => nsf,
                                      y => zf
                                 );
      and_ov    :  and2 port map (
                                      a => sf,
                                      b => din(7),
                                      y => ov
                  );
    nsf<= (not sf);                  
    dout(7)<=sf;  
    flagi(3)<=cf;
    flagi(2)<=zf;
    flagi(1)<=sf;
    flagi(0)<=ov;

end neg_instr_arch;
